? 2001 fairchild semiconductor corporation ds500151 www.fairchildsemi.com march 1999 revised july 2001 74lvt16244 ? 74lvth16244 low voltage16-bit buffer/line driver with 3-state outputs 74lvt16244 74lvth16244 low voltage16-bit buffer/line driver with 3-state outputs general description the lvt16244 and lvth16244 contain sixteen non-invert- ing buffers with 3-state outputs designed to be employed as a memory and address driver, clock driver, or bus ori- ented transmitter/receiver. the device is nibble controlled. individual 3-state control inputs can be shorted together for 8-bit or 16-bit operation. the lvth16244 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. these buffers and line drivers are designed for low-voltage (3.3v) v cc applications, but with the capability to provide a ttl interface to a 5v environment. the lvt16244 and lvth16244 are fabricated with an advanced bicmos technology to achieve high speed operation similar to 5v abt while maintaining a low power dissipation features input and output interface capability to systems at 5v v cc bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74lvth16244), also available without bushold feature (74lvt16244). live insertion/extraction permitted power up/down high impedance provides glitch-free bus loading outputs source/sink ? 32 ma/ + 64 ma functionally compatible with the 74 series 16244 latch-up performance exceeds 500 ma esd performance: human-body model > 2000v machine model > 200v charged-drive model > 1000v also packaged in plastic fine-pitch ball grid array (fbga) ordering code: note 1: bga package available in tape and reel only. note 2: device also available in tape and reel. specify by appending suffix letter ?x? to the ordering code. logic symbol order number package number package description 74lvt16244gx (note 1) bga54a (preliminary) 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide [tape and reel] 74lvt16244mea (note 2) ms48a 48-lead small shrink outline package (ssop), jedec mo-118, 0.300" wide 74lvt16244mtd (note 2) mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide 74lvth16244gx (note 1) bga54a 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide [tape and reel] 74lvth16244mea (note 2) ms48a 48-lead small shrink outline package (ssop), jedec mo-118, 0.300" wide 74lvth16244mtd (note 2) mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide
www.fairchildsemi.com 2 74lvt16244 74lvth16244 connection diagrams pin assignment for ssop and tssop pin assignment for fbga (top thru view) logic diagram pin descriptions fbga pin assignments truth table h = high voltage level l = low voltage level x = immaterial z = high impedance functional description the lvt16244 and lvth16244 contain sixteen non-invert- ing buffers with 3-state outputs. the device is nibble (4-bits) controlled with each nibble functioning identically, but independent of the other. the control pins can be shorted together to obtain full 16-bit operation. pin names description oe n output enable inputs (active low) i 0 ? i 15 inputs o 0 ? o 15 outputs nc no connect 123456 a o 0 nc oe 1 oe 2 nc i 0 b o 2 o 1 nc nc i 1 i 2 c o 4 o 3 v cc v cc i 3 i 4 d o 6 o 5 gnd gnd i 5 i 6 e o 8 o 7 gnd gnd i 7 i 8 f o 10 o 9 gnd gnd i 9 i 10 g o 12 o 11 v cc v cc i 11 i 12 h o 14 o 13 nc nc i 13 i 14 j o 15 nc oe 4 oe 3 nc i 15 inputs outputs oe 1 i 0 ? i 3 o 0 ? o 3 ll l lh h hx z inputs outputs oe 2 i 4 ? i 7 o 4 ? o 7 ll l lh h hx z inputs outputs oe 3 i 8 ? i 11 o 8 ? o 11 ll l lh h hx z inputs outputs oe 4 i 12 ? i 15 o 12 ? o 15 ll l lh h hx z
3 www.fairchildsemi.com 74lvt16244 74lvth16244 absolute maximum ratings (note 3) recommended operating conditions note 3: absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximum rated conditions is not implied. note 4: i o absolute maximum rating must be observed. dc electrical characteristics symbol parameter value conditions units v cc supply voltage ? 0.5 to + 4.6 v v i dc input voltage ? 0.5 to + 7.0 v v o output voltage ? 0.5 to + 7.0 output in 3-state v ? 0.5 to + 7.0 output in high or low state (note 4) i ik dc input diode current ? 50 v i < gnd ma i ok dc output diode current ? 50 v o < gnd ma i o dc output current 64 v o > v cc output at high state ma 128 v o > v cc output at low state i cc dc supply current per supply pin 64 ma i gnd dc ground current per ground pin 128 ma t stg storage temperature ? 65 to + 150 c symbol parameter min max units v cc supply voltage 2.7 3.6 v v i input voltage 0 5.5 v i oh high level output current ? 32 ma i ol low level output current 64 ma t a free air operating temperature ? 40 + 85 c ? t/ ? v input edge rate, v in = 0.8v ? 2.0v, v cc = 3.0v 0 10 ns/v symbol parameter v cc t a = ? 40 c to + 85 c units conditions (v) min max v ik input clamp diode voltage 2.7 ? 1.2 v i i = ? 18 ma v ih input high voltage 2.7 ? 3.6 2.0 v v o 0.1v or v il input low voltage 2.7 ? 3.6 0.8 v v o v cc ? 0.1v v oh output high voltage 2.7 ? 3.6 v cc ? 0.2 v i oh = ? 100 a 2.7 2.4 i oh = ? 8 ma 3.0 2.0 i oh = ? 32 ma v ol output low voltage 2.7 0.2 v i ol = 100 a 2.7 0.5 i ol = 24 ma 3.0 0.4 i ol = 16 ma 3.0 0.5 i ol = 32 ma 3.0 0.55 i ol = 64 ma i i(hold) bushold input minimum drive 3.0 75 a v i = 0.8v (note 5) ? 75 v i = 2.0v i i(od) bushold input over-drive 3.0 500 a (note 6) (note 5) current to change state ? 500 (note 7) i i input current 3.6 10 a v i = 5.5v control pins 3.6 1v i = 0v or v cc data pins 3.6 ? 5v i = 0v 1v i = v cc i off power off leakage current 0 100 a0v v i or v o 5.5v i pu/pd power up/down 0 ? 1.5v 100 a v o = 0.5v to 3.0v 3-state current v i = gnd or v cc i ozl 3-state output leakage current 3.6 ? 5 av o = 0.5v i ozh 3-state output leakage current 3.6 5 av o = 3.0v i ozh + 3-state output leakage current 3.6 10 av cc < v o 5.5v
www.fairchildsemi.com 4 74lvt16244 74lvth16244 dc electrical characteristics (continued) note 5: applies to bushold versions only (lvth16244). note 6: an external driver must source at least the specified current to switch from low-to-high. note 7: an external driver must sink at least the specified current to switch from high-to-low. note 8: this is the increase in supply current for each input that is at the specified voltage level rather than v cc or gnd. dynamic switching characteristics (note 9) note 9: characterized in ssop package. guaranteed parameter, but not tested. note 10: max number of outputs defined as (n). n ? 1 data inputs are driven 0v to 3v. output under test held low. ac electrical characteristics note 11: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). capacitance (note 12) note 12: capacitance is measured at frequency f = 1 mhz, per mil-std-883, method 3012. symbol parameter v cc t a = ? 40 c to + 85 c units conditions (v) min max i cch power supply current 3.6 0.19 ma outputs high i ccl power supply current 3.6 5.0 ma outputs low i ccz power supply current 3.6 0.19 ma outputs disabled i ccz + power supply current 3.6 0.19 ma v cc v o 5.5v, outputs disabled ? i cc increase in power supply current 3.6 0.2 ma one input at v cc ? 0.6v (note 8) other inputs at v cc or gnd symbol parameter v cc t a = 25 c units conditions (v) min typ max c l = 50 pf, r l = 500 ? v olp quiet output maximum dynamic v ol 3.3 0.8 v (note 10) v olv quiet output minimum dynamic v ol 3.3 ? 0.8 v (note 10) symbol parameter t a = ? 40 c to + 85 c units c l = 50 pf, r l = 500 ? v cc = 3.3v 0.3v v cc = 2.7v min max min max t plh propagation delay data to output 1.2 3.5 1.2 3.9 ns t phl 1.2 3.5 1.2 3.9 t pzh output enable time 1.2 4.0 1.2 5.0 ns t pzl 1.2 5.0 1.2 6.5 t phz output disable time 2.0 4.7 2.0 5.2 ns t plz 1.5 4.2 1.5 4.4 t oshl output to output skew 1.0 1.0 ns t oslh (note 11) symbol parameter conditions typical units c in input capacitance v cc = 0v, v i = 0v or v cc 4pf c out output capacitance v cc = 3.0v, v o = 0v or v cc 8pf
5 www.fairchildsemi.com 74lvt16244 74lvth16244 physical dimensions inches (millimeters) unless otherwise noted 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide package number bga54a
www.fairchildsemi.com 6 74lvt16244 74lvth16244 physical dimensions inches (millimeters) unless otherwise noted (continued) 48-lead small shrink outline package (ssop), jedec mo-118, 0.300" wide package number ms48a
7 www.fairchildsemi.com 74lvt16244 74lvth16244 low voltage16-bit buffer/line driver with 3-state outputs physical dimensions inches (millimeters) unless otherwise noted (continued) 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd48 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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